Mitigation of undesired spectral images due to bandwidth mismatch in time-interleaved a/ds by sampling capacitance randomization

ABSTRACT

Described herein are techniques for mitigating bandwidth mismatch in time-interleaved (TI) analog-to-digital converters (ADC). The techniques described herein involve spreading the energy associated with spurious tones resulting from bandwidth mismatch across the frequency spectrum, thereby reducing the overall impact of each individual tone. In some embodiments, for example, the tones may disappear under the noise floor. Spreading the energy associated with the spurious tones can be achieved by increasing the periodicity of the phase oscillation. This, in turn, can be achieved by introducing, in the phase oscillation, artificial phase shifts in addition to the phase shifts arising due to bandwidth mismatch. In one example, increasing the periodicity of a phase oscillation from 4 phase samples to 8 phase samples can result in a reduction in the power of a tone as high as 7 dB.

CROSS REFERENCE TO RELATED APPLICATIONS

This Application claims priority under 35 U.S.C. § 119(e) to U.S.Provisional Application No. 63/320,748, entitled “MITIGATION OFUNDESIRED SPECTRAL IMAGES DUE TO BANDWIDTH MISMATCH IN TIME-INTERLEAVEDA/DS BY SAMPLING CAPACITANCE RANDOMIZATION” filed on Mar. 17, 2022,which is herein incorporated by reference in its entirety.

BACKGROUND

Time interleaved (TI) analog-to-digital converters (ADC) sample inputsignals using multiple ADC units in a time-multiplexed fashion. TI ADCsare used in a broad variety of applications, including in high-endinstrumentations, Radar and Lidar, and wireless infrastructure (e.g., 5Gcellular towers).

BRIEF SUMMARY

Some embodiments relate to a time-interleaved (TI) analog-to-digitalconverter (ADC), comprising: an input terminal; a set of N pathselectrically coupled to the input terminal, each path comprising asampler configured to sample an input signal appearing at the inputterminal, wherein N is a positive integer, wherein the N paths result ina phase oscillation of the input signal as appearing at the samplers,wherein the phase oscillation presents at most N phase values, andwherein the phase oscillation oscillates in accordance with a firstperiodicity; and control circuitry configured to control at least someof the N samplers to modify the phase oscillation of the input signal sothat the modified phase oscillation presents more than N phase values,and the modified phase oscillation oscillates in accordance with asecond periodicity greater than the first periodicity.

In some embodiments, controlling the at least some of the N samplers tomodify the phase oscillation of the input signal comprises controllingthe at least some of the N samplers so that: at a first oscillationcycle, the input signal as appearing at a first sampler of the Nsamplers presents a first phase value, and at a second oscillation cyclesubsequent to the first oscillation cycle, the input signal as appearingat the first sampler of the N samplers presents a second phase valuedifferent from the first phase value.

In some embodiments, controlling at least some of the N samplers tomodify the phase oscillation of the input signal further comprisescontrolling the at least some of the N samplers so that: at the firstoscillation cycle, the input signal as appearing at a second sampler ofthe N samplers presents a third phase value, and at the secondoscillation cycle, the input signal as appearing at the second samplerof the N samplers presents a fourth phase value different from the thirdphase value.

In some embodiments, a first sampler of the N samplers comprises Pswitches, wherein P is a positive integer, and wherein controlling theat least some of the N samplers to modify the phase oscillation of theinput signal further comprises: at the first oscillation cycle,controlling the first sampler to maintain a first subset of the Pswitches active.

In some embodiments, controlling at least some of the N samplers tomodify the phase oscillation of the input signal further comprises: atthe second oscillation cycle, controlling the first sampler to maintaina second subset of the P switches active, the second subset beingdifferent from the first subset.

In some embodiments, the second periodicity is at least twice the firstperiodicity.

In some embodiments, controlling at least some of the N samplers tomodify the phase oscillation of the input signal comprises performing aphase permutation of the phase oscillation.

In some embodiments, performing the phase permutation of the phaseoscillation comprises performing the phase permutation of the phaseoscillation in accordance with a prime number.

In some embodiments, performing the phase permutation of the phaseoscillation comprises performing the phase permutation of the phaseoscillation in accordance with a random or pseudo-random cadence.

In some embodiments, the control circuitry is configured to clock the Nsamplers so that each sampler samples the input signal appearing at theinput terminal within a different time interval.

Some embodiments relate to a method for controlling a time-interleaved(TI) analog-to-digital converter (ADC), comprising: receiving an inputsignal at each path of a set of N paths electrically coupled to an inputterminal, wherein N is a positive integer, each path comprising asampler configured to sample the input signal, wherein the N pathsresult in a phase oscillation of the input signal as appearing at thesamplers, wherein the phase oscillation presents at most N phase values,and wherein the phase oscillation oscillates in accordance with a firstperiodicity; sampling the input signal with each sampler of the Nsamplers; and controlling at least some of the N samplers to modify thephase oscillation of the input signal so that the modified phaseoscillation presents more than N phase values, and the modified phaseoscillation oscillates in accordance with a second periodicity greaterthan the first periodicity.

In some embodiments, controlling the at least some of the N samplers tomodify the phase oscillation of the input signal comprises controllingthe N samplers so that: at a first oscillation cycle, the input signalas appearing at a first sampler of the N samplers presents a first phasevalue, and at a second oscillation cycle subsequent to the firstoscillation cycle, the input signal as appearing at the first sampler ofthe N samplers presents a second phase value different from the firstphase value.

In some embodiments, controlling the at least some of the N samplers tomodify the phase oscillation of the input signal further comprisescontrolling the N samplers so that: at the first oscillation cycle, theinput signal as appearing at a second sampler of the N samplers presentsa third phase value, and at the second oscillation cycle, the inputsignal as appearing at the second sampler of the N samplers presents afourth phase value different from the third phase value.

In some embodiments, a first sampler of the N samplers comprises Pswitches, wherein P is a positive integer, and wherein controlling theat least some of the N samplers to modify the phase oscillation of theinput signal further comprises: at the first oscillation cycle,controlling the first sampler to maintain a first subset of the Pswitches active.

In some embodiments, controlling the at least some of the N samplers tomodify the phase oscillation of the input signal further comprises: atthe second oscillation cycle, controlling the first sampler to maintaina second subset of the P switches active, the second subset beingdifferent from the first subset.

In some embodiments, the second periodicity is at least twice the firstperiodicity.

In some embodiments, controlling the at least some of the N samplers tomodify the phase oscillation of the input signal comprises performing aphase permutation of the phase oscillation.

In some embodiments, performing the phase permutation of the phaseoscillation comprises performing the phase permutation of the phaseoscillation in accordance with a prime number.

In some embodiments, performing the phase permutation of the phaseoscillation comprises performing the phase permutation of the phaseoscillation in accordance with a random or pseudo-random cadence.

In some embodiments, sampling the input signal with each sampler of theN samplers comprises clocking the N samplers so that each samplersamples the input signal within a different time interval.

The foregoing summary is provided by way of illustration and is notintended to be limiting.

BRIEF DESCRIPTION OF DRAWINGS

The accompanying drawings are not intended to be drawn to scale. In thedrawings, each identical or nearly identical component that isillustrated in various figures is represented by a like numeral. Forpurposes of clarity, not every component may be labeled in everydrawing.

FIG. 1A is a block diagram of a time interleaved (TI) analog-to-digitalconverters (ADC) suffering from bandwidth mismatch, in accordance withsome embodiments.

FIG. 1B is a plot illustrating clock signals for timing the operation ofthe TI ADC of FIG. 1A, in accordance with some embodiments.

FIG. 1C is a plot illustrating the amplitude response and the phaseresponse associated with some of the paths of the TI ADC of FIG. 1A, inaccordance with some embodiments.

FIG. 1D is a plot illustrating the amplitude response associated withthe TI ADC of FIG. 1A, in accordance with some embodiments.

FIG. 2A is a plot illustrating a phase oscillation associated with theTI ADC of FIG. 1A, in accordance with some embodiments.

FIG. 2B is a plot illustrating how the phase of the input signal jumpsbetween different paths of the TI ADC of FIG. 1A, in accordance withsome embodiments.

FIG. 3A is a block diagram of a differential TI ADC configured tomitigate bandwidth mismatch, in accordance with some embodiments.

FIG. 3B is a plot illustrating control signals for timing the operationof the TI ADC of FIG. 3A, in accordance with some embodiments.

FIG. 3C is a block diagram of a single-ended TI ADC configured tomitigate bandwidth mismatch, in accordance with some embodiments.

FIG. 4A is a block diagram illustrating a pseudo random noise generatorin addition to the single-ended TI ADC of FIG. 3C, in accordance withsome embodiments.

FIG. 4B is a plot illustrating control signals for timing the operationof the TI ADC of FIG. 4A, in accordance with some embodiments.

FIG. 4C is a diagram illustrating a circuit for varying the capacitanceof a sampler, in accordance with some embodiments.

FIG. 5A is a plot illustrating a technique for extending the periodicityof a phase oscillation, in accordance with some embodiments.

FIG. 5B illustrates the periodicity of a phase oscillation before andafter modification using a first example, in accordance with someembodiments.

FIG. 5C is a plot illustrating a phase oscillation before modificationusing the first example, in accordance with some embodiments.

FIG. 5D is a plot illustrating an amplitude response associated with thephase oscillation of FIG. 5C, in accordance with some embodiments.

FIG. 5E is a plot illustrating a phase oscillation after modificationusing the first example, in accordance with some embodiments.

FIG. 5F is a plot illustrating an amplitude response associated withphase oscillation after modification using the first example, inaccordance with some embodiments.

FIG. 6A illustrates the periodicity of a phase oscillation before andafter modification using a second example, in accordance with someembodiments.

FIG. 6B is a plot illustrating a phase oscillation before modificationusing the second example, in accordance with some embodiments.

FIG. 6C is a plot illustrating an amplitude response associated with thephase oscillation of FIG. 6B, in accordance with some embodiments.

FIG. 6D is a plot illustrating a phase oscillation after modificationusing the second example, in accordance with some embodiments.

FIG. 6E is a plot illustrating an amplitude response associated withphase oscillation after modification using the second example, inaccordance with some embodiments.

FIG. 7A illustrates the periodicity of a phase oscillation before andafter modification using a third example, in accordance with someembodiments.

FIG. 7B is a plot illustrating a phase oscillation before modificationusing the third example, in accordance with some embodiments.

FIG. 7C is a plot illustrating an amplitude response associated with thephase oscillation of FIG. 7B, in accordance with some embodiments.

FIG. 7D is a plot illustrating a phase oscillation after modificationusing the third example, in accordance with some embodiments.

FIG. 7E is a plot illustrating an amplitude response associated withphase oscillation after modification using the third example, inaccordance with some embodiments.

FIG. 8A is a plot illustrating the amplitude response of a TI ADC beforemodification using the third example, in accordance with someembodiments.

FIG. 8B is a plot illustrating the amplitude response of a TI ADC aftermodification using the third example, in accordance with someembodiments.

DETAILED DESCRIPTION I. Overview

The inventor has recognized and appreciated that time interleaved (TI)analog-to-digital converters (ADC) suffer from four types ofmismatch—offset mismatch, gain mismatch, time skew mismatch andbandwidth mismatch. Collectively, these phenomena degrade the integrityof the output signal, and as a result, the performance of the TI ADC.The inventor has developed techniques for mitigating bandwidth mismatch,the type of mismatch that affects the integrity of the output signal themost in most circumstances.

Bandwidth mismatch occurs because the paths that connect the inputterminal of a TI ADC to the various samplers present different timeconstants (e.g., RC). In some circumstances, the major contributor isthe fact that the sampling switches present different values ofresistance and/or capacitance. Bandwidth mismatch results in a phaseoscillation across the input terminals of the samplers. The phaseoscillation, in turn, gives rise to spurious tones in the spectralresponse of the converter that are substantially above the noise floor.The presence of these tones may be unacceptable in some contexts (e.g.,in high-end instrumentations, Radar and Lidar, and wirelessinfrastructure).

The techniques developed by the inventor and described herein involvespreading the energy associated with the spurious tones across thefrequency spectrum, thereby reducing the overall impact of individualtones. In some embodiments, for example, the tones may disappear underthe noise floor. Spreading the energy associated with the spurious tonescan be achieved by increasing the periodicity of the phase oscillation.This, in turn, can be achieved by introducing, in the phase oscillation,artificial phase shifts in addition to the phase shifts arising due tobandwidth mismatch. In one example, increasing the periodicity of aphase oscillation from 4 phase samples to 8 phase samples can result ina reduction in the power of a tone as high as 7 dB.

II. Bandwidth Mismatch

Bandwidth mismatch is a result of the fact that the paths that connectthe input terminal of a TI ADC to the various samplers inevitablypresent different time constants. FIG. 1 is a block diagram illustratinga TI ADC that suffers from bandwidth mismatch. TI ADC 100 includes aninput buffer 102, an input terminal 104, and a plurality of paths (fourpaths in this example, though more or fewer paths are also possible).Each path includes a sampler 106 and multiple ADCs 108 connected to thesampler. For example, path 105 includes a sampler 106 and ADCs 108 ₁,108 ₂ and 108 ₃. Having multiple paths each including multiple ADCsenables the TI ADC to sample signals at rates beyond what is possiblewith conventional ADCs. In this example, the input voltage appearing atthe input terminal 104 is voltage V_(in). Control circuitry 110generates the clock signals (ck1, ck2, ck3 and ck4) used to time theoperation of TI ADC 100. Examples of the clock signals are illustratedin FIG. 1B. Here, a clock having a high value indicates that thecorresponding sampler 106 is supposed to sample the input signal. Bycontrast, a clock having a low value indicates that the correspondingsampler 106 is not supposed to sample the input signal. Other logics arealso possible. As can be appreciated from FIG. 1B, control circuitry 110controls the TI ADC so that each sampler samples the input signal at adifferent time interval, thus providing the desired time interleavingeffect that enables higher sampling rates.

Referring back to FIG. 1A, each path presents a certain resistance andcapacitance, which results from the combination of the resistance andcapacitance of the conductive traces and the input resistance of thesamplers. In theory, the TI ADC is designed so that the resistances andcapacitances of the various paths are perfectly matched. In practice,however, the resistances and/or capacitance are slightly mismatched dueto inevitable variations in the manufacturing processes. Variations inthe input resistance and/or capacitance of the samplers can beparticularly serious. In some circumstances, even the slightestvariation in input resistance or capacitance (e.g., in the order of0.5%) can produce unacceptable results.

The variations in resistance and capacitance described above are whatcauses bandwidth mismatch. As a result, each path exhibits a differentfrequency response to input signals. FIG. 1C is a plot illustrating theamplitude response and the phase response associated with some of thepaths of the TI ADC of FIG. 1A. These plots illustrate the amplituderesponse and phase response of three representative paths of the fourpaths of FIG. 1A. As can be appreciated from the top plot, each pathexhibits a different frequency bandwidth. Further, as can be appreciatedfrom the bottom plot, each path exhibits a different frequency at whichthe convexity of the corresponding phase is inverted. Collectively,these effects result in the formation of spurious tones, although theimpact of the phase response tends to be larger than the impact of theamplitude response because, at least in some embodiments, the samplingrate of one sampler (e.g., 10 GHz) is lower than the cut-off frequencyof the path (e.g., 25 GHz). Examples of these tones are depicted in FIG.1D. In this example, although the input signal exhibits a singlefrequency tone (the input frequency), the signal spectrum furtherexhibits spurious tones, which arise due to the differences in thefrequency responses shown in FIG. 1C. These tones can seriously degradethe performance of the TI ADC.

The mismatch in the amplitude and phase responses associated with thedifferent paths gives rise to a phase oscillation. FIG. 2A is a plotthat illustrates how the phase of the TI ADC of FIG. 1A varies overtime. As can be appreciated from this figure, the overall phaseassociated with the signals appearing at the inputs the samplerspresents a cyclical behavior. Here, the TI ADC oscillates in accordancewith the following values: Φ1, Φ2, Φ3 and Φ4. Φ1 represents the phaseassociated with the first path of the TI ADC, Φ2 represents the phaseassociated with the second path, Φ3 represents the phase associated withthe third path, and Φ4 represents the phase associated with the fourthpath. The phase shown in FIG. 2A oscillates because, as differentsamplers are activated in a sequential fashion, the phase of thecurrently activated sampler is switched from one value to another. Inessence, as further shown in FIG. 2B, the phase cycles in accordancewith the following sequence: Φ1, Φ2, Φ3, Φ4, Φ1, Φ2, Φ3, Φ4, Φ1, Φ2, Φ3,Φ4 . . . Here, the periodicity of the phase oscillation is four samples.Every four samples, the phase oscillation repeats itself. It is thisphase oscillation that creates the spurious tones illustrated in FIG.1D.

III. Mitigation of Bandwidth Mismatch

Described herein are techniques for mitigating bandwidth mismatch in TIADCs. In some embodiments, this may be accomplished by spreading theenergy associated with the spurious tones across the frequency spectrum.In this way, the overall impact of each individual tone is reducedsubstantially. In some embodiments, for example, the tones may disappearunder the noise floor. Spreading the energy associated with the spurioustones can be achieved by increasing the periodicity of the phaseoscillation discussed above. This, in turn, can be achieved byintroducing artificial phase shifts in addition to the phase shiftsarising due to bandwidth mismatch.

In one example, a TI ADC has a set of N paths electrically coupled tothe input terminal (e.g., four paths in the example of FIG. 1A). The Npaths result in a phase oscillation of the input signal as appearing atthe samplers, where the phase oscillation presents at most N phasevalues (e.g., Φ1, Φ2, Φ3, Φ4). The phase oscillation oscillates inaccordance with a first periodicity (a periodicity of four phase valuesin the example of FIG. 1A). The techniques described herein involvecontrolling at least some of the N samplers to modify the phaseoscillation of the input signal so that the modified phase oscillationpresents more than N phase values. As a result, the modified phaseoscillation oscillates in accordance with a second periodicity greaterthan the first periodicity (e.g., a periodicity greater than four phasevalues).

FIG. 3A is a block diagram of a differential TI ADC arranged in thismanner. Each path of the TI ADC includes a pair of switches SW1, a pairof switches SW2, switches SWe and a pair of sampling capacitors Cs. Thetiming with which the switches are activated and deactivated in someembodiments is illustrated in FIG. 3B. The signals depicted in FIG. 3Bdictate the sample and hold operation of the TI ADC. FIG. 3C representsa single-ended implementation of a path of the TI ADC. The timing of thesampling is determined by the opening of the switches SWe. The mainsource of bandwidth mismatch is the on-resistance of the switches SW1,tied to a terminal of sampling capacitors Cs.

In some embodiments, increasing the periodicity of the phase oscillationfrom the first periodicity to the second periodicity can be accomplishedby introducing additional capacitors in parallel to the capacitors Cs,and by varying the capacitances of these additional capacitors inaccordance with random or pseudo random codes (thereby changing the timeconstant RC). FIG. 4A illustrates a diagram of a TI ADC path having onesuch parallel capacitor (Cr), the capacitance of which is set by apseudo random noise generator (PN). FIG. 4B is a plot illustratingcontrol signals for timing the operation of the circuit of FIG. 4A. Inaccordance with the plot of FIG. 4B, the total value of the samplingcapacitor Cs of each of path can be adjusted. The total value of Cs ischanged frequently, possibly each time a new sample is captured asdepicted in FIG. 4B. However, in some embodiments, a sampling capacitorCs need not be updated whenever a new sample is captured. Thus, when Csis varied, the corresponding bandwidth mismatch varies accordingly, andthe original periodic sequence of fixed bandwidth mismatches is replacedby a random sequence of ever-changing bandwidth mismatches. As a result,correlation among the sampled input waveform is reduced, thussubstantially improving the spurious free dynamic range (SFDR) of the TIADC.

In some embodiments, the total sampling capacitance can be realized byshunting a main sampling capacitor (having capacitance of Cs−δC/2(slightly smaller than the original Cs), with an additional smallcapacitor Cr the value of which is varied by the random digital code PN.Here, δC determines the desired range of capacitance variation. Thenominal value of Cr can be made adjustable from 0 to δC. As result, thetotal value of the sampling capacitance can be varied between Cs−δC/2and CS+δC/2.

In some embodiments, varying the capacitance of a sampler may involveproviding a sampler with multiple capacitors, and activating onlysub-sets of these capacitors in a randomized (or pseudo-randomized)fashion. FIG. 4C is a diagram illustrating a circuit for varying thecapacitance of a sampler, in accordance with some embodiments. In thisexample, a sampler includes P capacitors Cu, which areconnected/disconnected from resistor R depending on the state of thecorresponding transistors T_(A1), T_(A2), T_(A3), T_(A4) and T_(AP), andare connected/disconnected from ground depending on the state of thecorresponding transistors T_(B1), T_(B2), T_(B3), T_(B4) and T_(BP). Insome embodiments, only a sub-set of M (<P) capacitors are activated,thereby providing an overall capacitance C=M×C_(u). By varying which Mcapacitors are activated in a randomized (or pseudo-randomized) fashion,capacitance C can be randomized.

A. EXAMPLE 1

In some embodiments, varying the sampling capacitors results in anincrease of the periodicity of the phase oscillation. An example of thisresult is depicted in FIG. 5A. Initially, the phase oscillation proceedsas in the example of FIG. 2B: the first phase value of the oscillationis Φ1, the second phase value of the oscillation is Φ2, and the thirdphase value of the oscillation is Φ3. Subsequently, instead ofproceeding to Φ4 as shown in FIG. 2B, the phase oscillation of FIG. 5Aproceeds to phase value Φ4 a, where Φ4 a is different from Φ4. This canbe accomplished by varying the capacitance of the fourth samplingcapacitor from its nominal value. Then, the phase oscillation proceedsto phase value Φ1 a, where Φ1 a is different from Φ1. This can beaccomplished by varying the capacitance of the first sampling capacitorfrom its nominal value. Then, the phase oscillation proceeds to phasevalue Φ2 b, where Φ2 b is different from Φ2. This can be accomplished byvarying the capacitance of the second sampling capacitor from itsnominal value. Then, the phase oscillation proceeds to phase value Φ3 b,where Φ3 b is different from Φ3. This can be accomplished by varying thecapacitance of the third sampling capacitor from its nominal value.Lastly, the phase oscillation proceeds to phase value Φ4. This can beaccomplished by setting the capacitance of the fourth sampling capacitorback to its nominal value. The phase oscillation then repeats itself.FIG. 5B provides a comparison between two TI ADCs each having fourpaths. In the top panel, the phase oscillation is unmodified andpresents a periodicity of four phase values. In the bottom panel, thephase oscillation is modified in accordance with the scheme of FIG. 5A,and as a result presents a periodicity of eight phase values.

FIG. 5C is a plot illustrating how the unmodified phase oscillationvaries over time, and FIG. 5D is a plot illustrating the correspondingspectrum. In this example, the phase oscillation gives rise to aspurious tone having an amplitude (−52 dB) several orders of magnitudeabove the noise floor. By contrast, FIG. 5E is a plot illustrating thephase of the oscillation when modified in accordance with the sequenceof FIG. 5B. FIG. 5F is a plot illustrating the corresponding spectrum.As can be appreciated by comparing FIG. 5C with FIG. 5E, the modifiedphase oscillation deviates from a sinusoidal oscillation to a greaterextent than the unmodified oscillation does. The result is that theenergy of the spurious tone shown in FIG. 5D is spread among severaladditional tones not otherwise present in the unmodified case. Each toneof FIG. 5F has an amplitude that is significantly lower than theamplitude of the tone of FIG. 5D, thus reducing the negative effects ofbandwidth mismatch on the performance of the TI ADC. The tone with thelargest amplitude is 7 dB less than the tone of FIG. 5D.

B. EXAMPLE 2

In another example, the sequence of phase values appearing at thesamplers may be varied in accordance with permutations of prime numbers.For instance, the sequence may be altered every five samples (five is aprime number). The inventor has appreciated that by varying the phasesequence in accordance with permutations of prime numbers leads tolarger periodicities. The result is that the energy of a spurious toneis spread to an even greater extent. FIG. 6A illustrates the periodicityof a phase oscillation before and after modification using a permutationof a prime number, in accordance with some embodiments. In this example,the periodicity is increased from four phase values (in the unmodifiedcase) to twenty phase values (in the modified case).

FIG. 6B is a plot illustrating how the unmodified phase oscillationvaries over time, and FIG. 6C is a plot illustrating the correspondingspectrum. In this example, the phase oscillation gives rise to aspurious tone having an amplitude of −50 dB. By contrast, FIG. 6D is aplot illustrating the phase of the oscillation when modified inaccordance with the sequence of FIG. 6A. FIG. 6E is a plot illustratingthe corresponding spectrum. As can be appreciated by comparing FIG. 6Cwith FIG. 6E, the energy of the spurious tone shown in FIG. 6C is spreadamong several additional tones. Each tone of FIG. 6E has an amplitudethat is significantly lower than the amplitude of the tone of FIG. 6C,thus reducing the negative effects of bandwidth mismatch on theperformance of the TI ADC. The tone with the largest amplitude is 5 dBless than the tone of FIG. 6C.

C. EXAMPLE 3

In yet another example, the sequence of phase values appearing at thesamplers may be varied in accordance with a random or pseudo-randomcadence. For instance, the sequence may be altered every five samples atone cycle, every three samples at the following cycle, every foursamples at the following cycles, etc. The inventor has appreciated thatby varying the phase sequence in accordance with a random orpseudo-random cadence leads to even larger periodicities than what isshown in the previous examples. The result is that the energy of aspurious tone is spread to an even greater extent. FIG. 7A illustratesthe periodicity of a phase oscillation before and after modificationusing a random or pseudo-random cadence, in accordance with someembodiments. In this example, the periodicity is increased from fourphase values (in the unmodified case) to twenty-six phase values (in themodified case).

FIG. 7B is a plot illustrating how the unmodified phase oscillationvaries over time, and FIG. 7C is a plot illustrating the correspondingspectrum. In this example, the phase oscillation gives rise to aspurious tone having an amplitude of −52 dB. By contrast, FIG. 7D is aplot illustrating the phase of the oscillation when modified inaccordance with the random cadence of FIG. 7A. FIG. 7E is a plotillustrating the corresponding spectrum. As can be appreciated bycomparing FIG. 7C with FIG. 7E, the energy of the spurious tone shown inFIG. 7C is spread among so many new tones that the majority of the tonesthat arise as a result disappears under the noise floor. This occursbecause of the random (or pseudo-random) nature of the scramblingprocess used in Example 3. The result is that the noise floor is raised.Some tones may still lie above the noise floor, but their amplitude issubstantially reduced. For example, the amplitude of the largest tone is−60 dB, which represents an 8 dB improvement over FIG. 7C.

FIGS. 8A and 8B are plots illustrating the amplitude response of a TIADC before and after modification using the third example, respectively.More specifically, the plots represent the ADC's SFDR as a function offrequency. The unmodified scenario presents tones with an SFDR of about60 dBFS. Upon application of the technique described in accordance withthe third example, the majority of the energy is spread across so manynew tones that the energy of these tones disappears under the noisefloor. As a result, the noise floor raises. Here, the largest tones havean SFDR of 70 dBFS, representing a 10 dB improvement over FIG. 8A.

VI. CONCLUSION

Accordingly, some embodiments relate to a TI ADC including a set of Npaths electrically coupled to an input terminal (e.g., terminal 104).Each path includes a sampler (e.g., sampler 106) configured to sample aninput signal (e.g., Vin) appearing at the input terminal. Due tobandwidth mismatch, the N paths result in a phase oscillation of theinput signal as appearing at the samplers, where the phase oscillationpresents at most N phase values. For example, the phase oscillation maypresent four phase values or less where the TI ADC includes four pathsas illustrated in the example of FIG. 1A. The phase oscillationoscillates in accordance with a first periodicity (e.g., four phasevalues in the example of FIG. 2A). Control circuitry is configured tocontrol at least some of the N samplers to modify the phase oscillationof the input signal so that the modified phase oscillation presents morethan N phase values. For example, the unmodified phase oscillation maypresent four phase values and the modified phase oscillation may presenteight phase values, twenty phase values or twenty-six phase values,among a few possible examples. Accordingly, the modified phaseoscillation oscillates in accordance with a second periodicity greaterthan the first periodicity. This increase in the periodicity of thephase oscillation spreads the energy of spurious tones across thefrequency spectrum.

In some embodiments, at a first oscillation cycle, the input signal asappearing at a first sampler of the N samplers presents a first phasevalue (e.g., Φ1 as shown at the bottom panel of FIG. 5B), and, at asecond oscillation cycle subsequent to the first oscillation cycle, theinput signal as appearing at the first sampler of the N samplerspresents a second phase value (e.g., Φ1 a as shown at the bottom panelof FIG. 5B) different from the first phase value.

Further, in some embodiments, at the first oscillation cycle, the inputsignal as appearing at a second sampler of the N samplers presents athird phase value (e.g., Φ2 as shown at the bottom panel of FIG. 5B),and, at the second oscillation cycle, the input signal as appearing atthe second sampler of the N samplers presents a fourth phase value(e.g., Φ2 b as shown at the bottom panel of FIG. 5B) different from thethird phase value.

Use of ordinal terms such as “first”, “second”, “third”, etc., in theclaims to modify a claim element does not by itself connote anypriority, precedence, or order of one claim element over another or thetemporal order in which acts of a method are performed, but are usedmerely as labels to distinguish one claim element having a certain namefrom another element having a same name (but for use of the ordinalterm) to distinguish the claim elements.

Also, the phraseology and terminology used herein is for the purpose ofdescription and should not be regarded as limiting. The use of“including”, “comprising”, “having”, “containing” or “involving” andvariations thereof herein, is meant to encompass the items listedthereafter and equivalents thereof as well as additional items.

The use of “coupled” or “connected” is meant to refer to circuitelements, or signals, that are either directly linked to one another orthrough intermediate components.

The terms “approximately”, “substantially,” and “about” may be used tomean within ±10% of a target value in some embodiments. The terms“approximately” and “about” may include the target value.

What is claimed is:
 1. A time-interleaved (TI) analog-to-digitalconverter (ADC), comprising: an input terminal; a set of N pathselectrically coupled to the input terminal, each path comprising asampler configured to sample an input signal appearing at the inputterminal, wherein N is a positive integer, wherein the N paths result ina phase oscillation of the input signal as appearing at the samplers,wherein the phase oscillation presents at most N phase values, andwherein the phase oscillation oscillates in accordance with a firstperiodicity; and control circuitry configured to control at least someof the N samplers to modify the phase oscillation of the input signal sothat the modified phase oscillation presents more than N phase values,and the modified phase oscillation oscillates in accordance with asecond periodicity greater than the first periodicity.
 2. The TI ADC ofclaim 1, wherein controlling the at least some of the N samplers tomodify the phase oscillation of the input signal comprises controllingthe at least some of the N samplers so that: at a first oscillationcycle, the input signal as appearing at a first sampler of the Nsamplers presents a first phase value, and at a second oscillation cyclesubsequent to the first oscillation cycle, the input signal as appearingat the first sampler of the N samplers presents a second phase valuedifferent from the first phase value.
 3. The TI ADC of claim 2, whereincontrolling at least some of the N samplers to modify the phaseoscillation of the input signal further comprises controlling the atleast some of the N samplers so that: at the first oscillation cycle,the input signal as appearing at a second sampler of the N samplerspresents a third phase value, and at the second oscillation cycle, theinput signal as appearing at the second sampler of the N samplerspresents a fourth phase value different from the third phase value. 4.The TI ADC of claim 2, wherein a first sampler of the N samplerscomprises P switches, wherein P is a positive integer, and whereincontrolling the at least some of the N samplers to modify the phaseoscillation of the input signal further comprises: at the firstoscillation cycle, controlling the first sampler to maintain a firstsubset of the P switches active.
 5. The TI ADC of claim 4, whereincontrolling at least some of the N samplers to modify the phaseoscillation of the input signal further comprises: at the secondoscillation cycle, controlling the first sampler to maintain a secondsubset of the P switches active, the second subset being different fromthe first subset.
 6. The TI ADC of claim 1, wherein the secondperiodicity is at least twice the first periodicity.
 7. The TI ADC ofclaim 1, wherein controlling at least some of the N samplers to modifythe phase oscillation of the input signal comprises performing a phasepermutation of the phase oscillation.
 8. The TI ADC of claim 7, whereinperforming the phase permutation of the phase oscillation comprisesperforming the phase permutation of the phase oscillation in accordancewith a prime number.
 9. The TI ADC of claim 7, wherein performing thephase permutation of the phase oscillation comprises performing thephase permutation of the phase oscillation in accordance with a randomor pseudo-random cadence.
 10. The TI ADC of claim 1, wherein the controlcircuitry is configured to clock the N samplers so that each samplersamples the input signal appearing at the input terminal within adifferent time interval.
 11. A method for controlling a time-interleaved(TI) analog-to-digital converter (ADC), comprising: receiving an inputsignal at each path of a set of N paths electrically coupled to an inputterminal, wherein N is a positive integer, each path comprising asampler configured to sample the input signal, wherein the N pathsresult in a phase oscillation of the input signal as appearing at thesamplers, wherein the phase oscillation presents at most N phase values,and wherein the phase oscillation oscillates in accordance with a firstperiodicity; sampling the input signal with each sampler of the Nsamplers; and controlling at least some of the N samplers to modify thephase oscillation of the input signal so that the modified phaseoscillation presents more than N phase values, and the modified phaseoscillation oscillates in accordance with a second periodicity greaterthan the first periodicity.
 12. The method of claim 11, whereincontrolling the at least some of the N samplers to modify the phaseoscillation of the input signal comprises controlling the N samplers sothat: at a first oscillation cycle, the input signal as appearing at afirst sampler of the N samplers presents a first phase value, and at asecond oscillation cycle subsequent to the first oscillation cycle, theinput signal as appearing at the first sampler of the N samplerspresents a second phase value different from the first phase value. 13.The method of claim 12, wherein controlling the at least some of the Nsamplers to modify the phase oscillation of the input signal furthercomprises controlling the N samplers so that: at the first oscillationcycle, the input signal as appearing at a second sampler of the Nsamplers presents a third phase value, and at the second oscillationcycle, the input signal as appearing at the second sampler of the Nsamplers presents a fourth phase value different from the third phasevalue.
 14. The method of claim 12, wherein a first sampler of the Nsamplers comprises P switches, wherein P is a positive integer, andwherein controlling the at least some of the N samplers to modify thephase oscillation of the input signal further comprises: at the firstoscillation cycle, controlling the first sampler to maintain a firstsubset of the P switches active.
 15. The method of claim 14, whereincontrolling the at least some of the N samplers to modify the phaseoscillation of the input signal further comprises: at the secondoscillation cycle, controlling the first sampler to maintain a secondsubset of the P switches active, the second subset being different fromthe first subset.
 16. The method of claim 11, wherein the secondperiodicity is at least twice the first periodicity.
 17. The method ofclaim 11, wherein controlling the at least some of the N samplers tomodify the phase oscillation of the input signal comprises performing aphase permutation of the phase oscillation.
 18. The method of claim 17,wherein performing the phase permutation of the phase oscillationcomprises performing the phase permutation of the phase oscillation inaccordance with a prime number.
 19. The method of claim 17, whereinperforming the phase permutation of the phase oscillation comprisesperforming the phase permutation of the phase oscillation in accordancewith a random or pseudo-random cadence.
 20. The method of claim 11,wherein sampling the input signal with each sampler of the N samplerscomprises clocking the N samplers so that each sampler samples the inputsignal within a different time interval.